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Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Document order number: MC33982/D Rev 7.0, 03/2004
Preliminary Information Single Intelligent High-Current Self-Protected Silicon High-Side Switch (2.0 m)
The 33982 is a self-protected silicon 2.0 m high-side switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. The 33982 is designed for harsh environments, and it includes self-recovery features. The device is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads.
33982
SINGLE HIGH-SIDE SWITCH 2.0 m
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Programming, control, and diagnostics are implemented via the Serial Peripheral Interface (SPI). A dedicated parallel input is available for alternate and pulse width modulation (PWM) control of the output. SPI programmable fault trip thresholds allow the device to be adjusted for optimal performance in the application. The 33982 is packaged in a power-enhanced 12 x 12 PQFN package with exposed tabs. Features * Single 2.0 m Max High-Side Switch with Parallel Input or SPI Control * 6.0 V to 27 V Operating Voltage with Standby Currents < 5.0 A * Output Current Monitoring Output with Two SPI-Selectable Current Ratios * SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time, Output-OFF Open Load Detection, Output ON/OFF Control, Watchdog Timeout, Slew Rates, and Fault Status Reporting * SPI Status Reporting of Overcurrent, Open and Shorted Loads, Overtemperature Shutdown, Undervoltage and Overvoltage Shutdown, Fail-Safe Terminal Status, and Program Status * Enhanced 16 V Reverse Polarity VPWR Protection
PNA SUFFIX CASE 1402-02 16-TERMINAL PQFN SCALE 1:1
ORDERING INFORMATION
Device MC33982PNA/R2 Temperature Range (TA) -40C to 125C Package 16 PQFN
Simplified Application Diagram 33982 Simplified Application Diagram
VDD
VDD
VDD 33982 VDD
VPWR VPWR GND
I/O I/O SO SCLK MCU CS SI I/O I/O A/D
FS WAKE SI SCLK CS HS SO RST IN CSNS FSI GND
LOAD
GND
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. (c) Motorola, Inc. 2004
PWRGND
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VDD
VPWR
Internal Regulator Programmable Switch Delay 0 ms-525 ms SPI 3.0 MHz Logic
Overvoltage Protection Selectable Slew Rate Gate Drive HS Selectable Current Limit 150 A or 100 A Selectable Current Detection Time 0.15 ms-155 ms Open Load Detection Overtemperature Detection Selectable Output Current Recopy 1/5400 or 1/40000 Selectable Overcurrent Detection 15 A-50 A
CS SCLK SO SI RST WAKE IN FS
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FSI
Programmable Watchdog 310 ms-2500 ms
GND
Figure 1. 33982 Simplified Internal Block Diagram
CSNS
33982 2
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Transparent Top View of Package
CSNS WAKE RST IN FS FSI CS SCLK SI VDD SO NC 1 2 3 4 5 13 6 7 GND 8 9 10 11 12
16 14 VPWR
HS
15
HS
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TERMINAL FUNCTION DESCRIPTION
Terminal 1 Terminal Name CSNS Formal Name Output Current Monitoring Definition This terminal is used to output a current proportional to the high-side output current and used externally to generate a ground-referenced voltage for the microcontroller to monitor output current. This terminal is used to input a logic [1] signal in order to enable the watchdog timer function. An internal clamp protects this terminal from high damaging voltages when the output is current limited with an external resistor. This input has an internal passive pull-down. This input terminal is used to initialize the device configuration and fault registers, as well as place the device in a low current sleep mode. The terminal also starts the watchdog timer when transitioning from logic LOW to logic HIGH. This terminal should not be allowed to be logic HIGH until VDD is in regulation. This terminal has an internal passive pull-down. The Input terminal is used to directly control the output. This input has an internal active pull-down and requires CMOS logic levels. This input may be configured via SPI. This is an open drain configured output requiring an external pull-up resistor to VDD for fault reporting. When a device fault condition is detected, this terminal is active LOW. Specific device diagnostic faults are reported via the SPI SO terminal. The value of the resistance connected between this terminal and ground determines the state of the output after a watchdog timeout occurs. Depending on the resistance value, either the output is OFF or ON. When the FSI terminal is connected to GND, the watchdog circuit and fail-safe operation are disabled. This terminal incorporates an active internal pull-up. This is an input terminal connected to a chip select output of a master microcontroller (MCU). The MCU determines which device is addressed (selected) to receive data by pulling the CS terminal of the selected device logic LOW, enabling SPI communication with the device. Other unselected devices on the serial link having their CS terminals pulled up logic HIGH disregard the SPI communication data sent. This input terminal is connected to the MCU providing the required bit shift clock for SPI communication. It transitions one time per bit transferred at an operating frequency, fSPI, defined by the communication interface. The 50 percent duty cycle CMOS-level serial clock signal is idle between command transfers. The signal is used to shift data into and out of the device.
2
WAKE
Wake
3
RST
Reset (Active Low)
4 5
IN
Serial Input
FS
Fault Status (Active Low)
6
FSI
Fail-Safe Input
7
CS
Chip Select (Active Low)
8
SCLK
Serial Clock
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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TERMINAL FUNCTION DESCRIPTION (continued)
Terminal 9 Terminal Name SI Formal Name Serial Input Definition This is a command data input terminal connected to the SPI Serial Data Output of the MCU or to the SO terminal of the previous device in a daisy chain of devices. The input requires CMOS logic level signals and incorporates an internal active pull-down. Device control is facilitated by the input's receiving the MSB first of a serial 8-bit control command. The MCU ensures data is available upon the falling edge of SCLK. The logic state of SI present upon the rising edge of SCLK loads that bit command into the internal command shift register. This is an external voltage input terminal used to supply power to the SPI circuit. In the event VDD is lost, an internal supply provides power to a portion of the logic, ensuring limited functionality of the device. This is an output terminal connected to the SPI Serial Data Input terminal of the MCU or to the SI terminal of the next device in a daisy chain of devices. This output will remain tri-stated (high impedance OFF condition) so long as the CS terminal of the device is logic HIGH. SO is only active when the CS terminal of the device is asserted logic LOW. The generated SO output signals are CMOS logic levels. SO output data is available on the falling edge of SCLK and transitions immediately on the rising edge of SCLK. This terminal may not be connected. This terminal is the ground for the logic and analog circuitry of the device. This terminal connects to the positive power supply and is the source input of operational power for the device. The VPWR terminal is a backside surface mount tab of the package. Protected high-side power output to the load. Output terminals must be connected in parallel for operation.
10
VDD
Digital Drain Voltage (Power)
11
SO
Serial Output
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12 13 14
NC GND VPWR
No Connect Ground Positive Power Supply
15, 16
HS
High-Side Output
33982 4
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MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted.
Rating Operating Voltage Range Steady-State VDD Supply Voltage Input/Output Voltage (Note 1) VDD VIN, RST, FSI, CSNS, SI, SCLK,
CS, FS
Symbol VPWR
Value -16 to 41 0 to 5.5 -0.3 to 7.0
Unit V
V V
SO Output Voltage (Note 1) WAKE Input Clamp Current
VSO ICL(WAKE) ICL(CSNS) IOUT ECL TSTG TJ RJC RJA VESD1 VESD2 TSOLDER
-0.3 to VDD +0.3 2.5 10 60 1.5 -55 to 150 -40 to 150 <1.0 20
V mA mA A J
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CSNS Input Clamp Current Output Current (Note 2) Output Clamp Energy (Note 3) Storage Temperature Operating Junction Temperature Thermal Resistance (Note 4) Junction to Case Junction to Ambient ESD Voltage Human Body Model (Note 5) Machine Model (Note 6) Terminal Soldering Temperature (Note 7)
C C C/W
V 2000 200 240
C
Notes 1. Exceeding voltage limits on IN, RST, FSI, CSNS, SI, SO, SCLK, CS, or FS terminals may cause a malfunction or permanent damage to the device. 2. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current using package thermal resistance is required. 3. Active clamp energy using single-pulse method (L = 16 mH, RL = 0, VPWR = 12 V, TJ = 150C). 4. 5. 6. 7. Device mounted on a 2s2p test board according to JEDEC JESD51-2. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ). ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ) and in accordance with the system module specification with a capacitor > 0.01 F connected from HS to GND. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device.
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33982 5
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STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
POWER INPUT
Battery Supply Voltage Range Full Operational VPWR Operating Supply Current Output ON, IOUT = 0 A VPWR Supply Current Output OFF, Open Load Detection Disabled, WAKE > 0.7 VDD, IPWR(SBY) - IPWR(SLEEP) - - VDD(ON) IDD(ON) - - IDD(SLEEP) VPWR(ON) VPWR(OVHYS) VPWR(UV) VPWR(UVHYS) VPWR(UVPOR) - 28 0.2 5.0 - - - - - 32 0.8 5.5 0.25 - 1.0 5.0 5.0 36 1.5 6.0 - 5.0 A V V V V V 4.5 - - 5.0 10 50 5.5 V mA - 5.0 A IPWR(ON) - - 20 mA VPWR 6.0 - 27 mA V
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RST = VLOGIC HIGH
Sleep State Supply Current (VPWR < 14 V, RST < 0.5 V, WAKE < 0.5 V) TJ = 25C TJ = 85C VDD Supply Voltage VDD Supply Current No SPI Communication 3.0 MHz SPI Communication VDD Sleep State Current Overvoltage Shutdown Overvoltage Shutdown Hysteresis Undervoltage Output Shutdown (Note 8) Undervoltage Hysteresis (Note 9) Undervoltage Power-ON Reset
Notes 8. Output will automatically recover to instructed state when VPWR voltage is restored to normal so long as the VPWR degradation level did not go below the undervoltage power-ON reset threshold. This applies to all internal device logic that is supplied by VPWR and assumes that the external VDD supply is within specification. 9. This applies when the undervoltage fault is not latched (IN = 0).
33982 6
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STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
POWER OUTPUT
Output Drain-to-Source ON Resistance (IOUT = 30 A, TJ = 25C) VPWR = 6.0 V VPWR = 10 V VPWRR = 13 V Output Drain-to-Source ON Resistance (IOUT = 30 A, TJ = 150C) VPWR = 6.0 V RDS(ON)150 - - - RDS(ON) - 2.0 4.0 A IOCH0 IOCH1 IOCL0 IOCL1 IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7 120 80 150 100 180 120 A 41 36 32 29 25 20 16 12 50 45 40 35 30 25 20 15 59 54 48 41 35 30 24 18 - - - 5.1 3.4 3.4 m RDS(ON)25 - - - - - - 3.0 2.0 2.0 m m
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VPWR = 10 V VPWR = 13 V Output Source-to-Drain ON Resistance (IOUT = 30 A, TJ = 25C) (Note 10) VPWR = -12 V Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V) SOCH = 0 SOCH = 1 Overcurrent Low Detection Levels (SOCL[2:0]) 000 001 010 011 100 101 110 111 Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V) DICR D2 = 0 DICR D2 = 1 Current Sense Ratio (CSR0) Accuracy Output Current 10 A 20 A 25 A 30 A 40 A 50 A CSR0 CSR1 CSR0_ACC
- -
1/5400 1/40000
- - %
-20 -14 -13 -12 -13 -13
- - - - - -
20 14 13 12 13 13
Notes 10. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR.
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STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
POWER OUTPUT (continued)
Current Sense Ratio (CSR1) Accuracy Output Current 10 A 20 A 25 A 30 A 40 A 50 A CSR1_ACC -25 -19 -18 -17 -18 -18 VCL(MAXCSNS) 4.5 IOLDC VOLD(THRES) 2.0 VCL -20 TSD 160 TSD(HYS) 5.0 175 - 190 20 - - 3.0 4.0 V 30 6.0 - 7.0 100 A V - - - - - - 25 19 18 17 18 18 V %
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Maximum Current Sense Clamp Voltage ICSNS = 15 mA Open Load Detection Current (Note 11) Output Fault Detection Threshold Output Programmed OFF Output Negative Clamp Voltage 0.5 A < = IOUT < = 2.0 A, Output OFF Overtemperature Shutdown (Note 12) TA = 125C, Output OFF Overtemperature Shutdown Hysteresis (Note 12)
C C
Notes 11. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF. 12. Guaranteed by process monitoring. Not production tested.
33982 8
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STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
CONTROL INTERFACE
Input Logic High Voltage (Note 13) Input Logic Low Voltage (Note 13) Input Logic Voltage Hysteresis (Note 14) Input Logic Pull-Down Current (SCLK, IN, SI)
RST Input Voltage Range
VIH VIL VIN(HYS) IDWN VRST CSO IDWN CIN VCL(WAKE)
0.7VDD - 100 5.0 4.5 - 100 -
- - 350 - 5.0 - 200 4.0
- 0.2VDD 750 20 5.5 20 400 12
V V mV A V pF k pF V
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SO, FS Tri-State Capacitance (Note 15) Input Logic Pull-Down Resistor (RST) and WAKE Input Capacitance (Note 15) WAKE Input Clamp Voltage (Note 16) ICL(WAKE) < 2.5 mA WAKE Input Forward Voltage ICL(WAKE) = -2.5 mA SO High-State Output Voltage IOH = 1.0 mA
FS, SO Low-State Output Voltage
7.0 VF(WAKE) -2.0 VSOH 0.8VDD VSOL - ISO(LEAK) -5.0 IUP 5.0 RFS RFSdis RFSoff RFSon - 6.0 30
-
14 V
-
-0.3 V
-
- V
IOL = -1.6 mA SO Tri-State Leakage Current
CS > 0.7 VDD
0.2
0.4 A
0
5.0 A
Input Logic Pull-Up Current (Note 17)
CS, VIN > 0.7VDD
-
20 k
FSI Input Pin External Pull-Down Resistance FSI Disabled, HS Indeterminate FSI Enabled, HS OFF FSI Enabled, HS ON
0 10 -
1.0 14 -
Notes 13. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN, and WAKE input signals. The WAKE and RST signals may be supplied by a derived voltage reference to VPWR. 14. 15. 16. 17. Parameter is guaranteed by process monitoring but is not production tested. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested. The current must be limited by a series resistance when using voltages > 7.0 V. Pull-up current is with CS OPEN. CS has an active internal pull-up to VDD.
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DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
POWER OUTPUT TIMING
Output Rising Slow Slew Rate A (DICR D3 = 0) (Note 18) 9.0 V < VPWR < 16 V Output Rising Slow Slew Rate B (DICR D3 = 0) (Note 19) 9.0 V < VPWR < 16 V Output Rising Fast Slew Rate A (DICR D3 = 1) (Note 18) 9.0 V < VPWR < 16 V SRRA_FAST 0.4 SRRB_FAST 0.03 SRFA_SLOW 0.2 SRFB_SLOW 0.03 SRFA_FAST 0.8 SRFB_FAST 0.1 0.35 1.2 2.0 4.0 V/s 0.1 0.3 V/s 0.6 1.2 V/s 0.1 1.2 V/s 1.0 4.0 V/s SRRB_SLOW 0.03 0.1 0.3 V/s SRRA_SLOW 0.2 0.6 1.2 V/s V/s
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Output Rising Fast Slew Rate B (DICR D3 = 1) (Note 19) 9.0 V < VPWR < 16 V Output Falling Slow Slew Rate A (DICR D3 = 0) (Note 18) 9.0 V < VPWR < 16 V Output Falling Slow Slew Rate B (DICR D3 = 0) (Note 19) 9.0 V < VPWR < 16 V Output Falling Fast Slew Rate A (DICR D3 = 1) (Note 18) 9.0 V < VPWR < 16 V Output Falling Fast Slew Rate B (DICR D3 = 1) (Note 19) 9.0 V < VPWR < 16 V
Notes 18. Rise and Fall Slew Rates A measured across a 5.0 resistive load at high-side output = 0.5 V to VPWR -3.5 V. These parameters are guaranteed by process monitoring. 19. Rise and Fall Slow Slew Rates B measured across a 5.0 resistive load at high-side output = 0.5 V to VPWR -3.5 V. These parameters are guaranteed by process monitoring.
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DYNAMIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
POWER OUTPUT TIMING (continued)
Output Turn-ON Delay Time in Fast/Slow Slew Rate (Note 20) DICR = 0, DICR = 1 Output Turn-OFF Delay Time in Slow Slew Rate Mode (Note 21) DICR = 0 Output Turn-OFF Delay Time in Fast Slew Rate Mode (Note 21) DICR = 1 tDLY_FAST(OFF) 10 fPWM - 60 300 200 - Hz ms tDLY_SLOW(OFF) 20 230 500 s tDLY(ON) 1.0 18 100 s s
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Direct Input Switching Frequency (DICR D3 = 0) Overcurrent Detection Blanking Time (OCLT[1:0]) 00 01 10 11 Overcurrent High Detection Blanking Time
CS to CSNS Valid Time (Note 22)
tOCL0 tOCL1 tOCL2 tOCL3 tOCH
CNSVAL
108 7.0 0.8 0.08 1.0 -
155 10 1.2 0.15 10 -
202 13 1.6 0.25 20 10 s s ms
Output Switching Delay Time (OSD[2:0]) 000 001 010 011 100 101 110 111 Watchdog Timeout (WD[1:0]) (Note 23) 00 01 10 11
tOSD0 tOSD1 tOSD2 tOSD3 tOSD4 tOSD5 tOSD6 tOSD7
tWDTO0 tWDTO1 tWDTO2 tWDTO3
- 52 105 157 210 262 315 367
0 75 150 225 300 375 450 525
- 95 195 293 390 488 585 683 ms
434 207 1750 875
620 310 2500 1250
806 403 3250 1625
Notes 20. Turn-ON delay time measured from rising edge of any signal (IN, SCLK, CS) that would turn the output ON to VOUT = 0.5 V with RL = 5.0 resistive load. 21. Turn-OFF delay time measured from falling edge of any signal (IN, SCLK, CS) that would turn the output OFF to VOUT = VPWR -0.5 V with RL = 5.0 resistive load. 22. 23. Time necessary for the CSNS to be within 5% of the targeted value. Watchdog timeout delay measured from the rising edge of WAKE to RST from a sleep state condition to output turn-ON with the output driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of tWDTO is consistent for all configured watchdog timeouts.
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DYNAMIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
SPI INTERFACE CHARACTERISTICS
Recommended Frequency of SPI Operation Required Low State Duration for RST (Note 24) Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note 25) Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note 25) Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (Note 25)
fSPI tWRST tCS tENBL tLEAD tWSCLKh tWSCLKl tLAG tSI(SU) tSI(HOLD) tRSO
- - - - - - - - - -
- 50 - - 50 - - 50 25 25
3.0 167 300 5.0 167 167 167 167 83 83
MHz ns ns s ns ns ns ns ns ns ns
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Required High State Duration of SCLK (Required Setup Time) (Note 25) Required Low State Duration of SCLK (Required Setup Time) (Note 25) Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (Note 25) SI to Falling Edge of SCLK (Required Setup Time) (Note 26) Falling Edge of SCLK to SI (Required Setup Time) (Note 26) SO Rise Time CL = 200 pF SO Fall Time CL = 200 pF SI, CS, SCLK, Incoming Signal Rise Time (Note 26) SI, CS, SCLK, Incoming Signal Fall Time (Note 26) Time from Falling Edge of CS to SO Low Impedance (Note 27) Time from Rising Edge of CS to SO High Impedance (Note 28) Time from Rising Edge of SCLK to SO Data Valid (Note 29) 0.2 VDD SO 0.8 VDD, CL = 200 pF Notes 24. 25. 26. 27. 28. 29.
-
25
50 ns
tFSO
- 25 - - - 65 50 50 50 145 145
tRSI tFSI tSO(EN) tSO(DIS) tVALID
- - - -
ns ns ns ns ns
-
65
105
RST low duration measured with outputs enabled and going to OFF or disabled condition. Maximum setup time required for the 33982 is the minimum guaranteed time needed from the microcontroller. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for output status data to be available for use at SO. 1.0 k on pull-up on CS. Time required for output status data to be terminated at SO. 1.0 k on pull-up on CS. Time required to obtain valid data out from SO following the rise of SCLK.
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Timing Diagrams
CS
VPWR VPWR VPWR - 0.5V VPWR -0.5 V VPWR - 3V VPWR -3.5 V
SRRB SRrB
SRFB SRfB SRFA SRfA
SRRA SRrA
0.5V 0.5
V t DLY(OFF) Tdly(off)
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tDLY(ON) Tdly(on)
Figure 2. Output Slew Rate and Time Delays
IOCHx ILOAD1
Load Current IOCLx
ILOAD1
tOCH Time tOCLx Figure 3. Overcurrent Shutdown
IOCH0 IOCH1 IOCL0
IOCL1
Load Current
IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7
Time
tOCHx tOCL3 tOCL2 tOCL1 tOCL0
Figure 4. Overcurrent Low and High Detection
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VIH V
IH
RSTB RST
0.2 VDD 0.2 VDD
TwRSTB
VIL TCSB t CS
VIL
tWRST
tENBL
TENBL
0.7 VDD 0.7VDD CS CSB 0.7 VDD 0.7VDD tTlead LEAD tWSCLKh TwSCLKh tRSI
TrSI
VIH V
IH
VIL V
IL
SCLK SCLK
0.7 VDD 0.7VDD 0.2 VDD
0.2VDD
tLAG Tlag
VIH VIH VIL V
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tSI(SU) TSIsu
tWSCLKl TwSCLKl
IL
tSI(HOLD) TSI(hold)
tTfSI FSI
VIH V Valid Don't Care
IH
SI SI
Don't Care
0.7 VDD 0.7 VDD 0.2VDD 0.2 VDD
Valid
Don't Care
VIH VIL
Figure 5. Input Timing Switching Characteristics
tRSI
tFSI
TrSI
3.5 3.5V V
TfSI VOH VOH 50% 1.0V 1.0 V VOL VOL
SCLK SCLK
tSO(EN)
TdlyLH
SO SO
0.7 VDD VDD
VOH VOH VOL VOL
0.2 VDD 0.2 VDD TrSO tRSO TVALID tVALID
Low-to-High Low to High
SO
SO
0.7 VDD High to Low High-to-Low 0.7 VDD
TfSO tFSO
VOH VOH
TdlyHL
tSO(DIS)
0.2VDD 0.2 VDD
VOL VOL
Figure 6. SCLK Waveform and Valid SO Data Delay Time
33982 14
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33982 is a self-protected silicon 2.0 m high-side switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. The 33982 is designed for harsh environments, and it includes self-recovery features. The device is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. Programming, control, and diagnostics are implemented via the Serial Peripheral Interface (SPI). A dedicated parallel input is available for alternate and pulse width modulation (PWM) control of the output. SPI programmable fault trip thresholds allow the device to be adjusted for optimal performance in the application. The 33982 is packaged in a power-enhanced 12 x 12 PQFN package with exposed tabs.
FUNCTIONAL DESCRIPTION
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SPI Protocol Description
The SPI interface has a full duplex, three-wire synchronous data transfer with four I/O lines associated with it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO), and Chip Select (CS). The SI/SO terminals of the 33982 follow a first-in first-out (D7/D0) protocol with both input and output words transferring the most significant bit (MSB) first. All inputs are compatible with 5.0 V CMOS logic levels. The SPI lines perform the following functions: Serial Clock (SCLK) The SCLK terminal clocks the internal shift registers of the 33982 device. The serial input terminal (SI) accepts data into the input shift register on the falling edge of the SCLK signal while the serial output terminal (SO) shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important that the SCLK terminal be in a logic LOW state whenever CS makes any transition. For this reason, it is recommended that the SCLK terminal be in a logic [0] state whenever the device is not accessed (CS logic [1] state). SCLK has an internal pull-down, IDWN. When CS is logic [1], signals at the SCLK and SI terminals are ignored and SO is tri-stated (high impedance). (See Figure 7 and Figure 8 on page 16.) Serial Interface (SI) This is a serial interface (SI) command data input terminal. SI instruction is read on the falling edge of SCLK. An 8-bit stream
of serial data is required on the SI terminal, starting with D7 to D0. The internal registers of the 33982 are configured and controlled using a 4-bit addressing scheme, as shown in Table 1, page 16. Register addressing and configuration are described in Table 2, page 17. The SI input has an internal pulldown, IDWN. Serial Output (SO) The SO terminal is a tri-stateable output from the shift register. The SO terminal remains in a high-impedance state until the CS terminal is put into a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, and the state of the key inputs. The SO terminal changes states on the rising edge of SCLK and reads out on the falling edge of SCLK. Fault and input status descriptions are provided in Table 8, page 19. Chip Select (CS) The CS terminal enables communication with the master microcontroller (MCU). When this terminal is in a logic [0] state, the device is capable of transferring information to and receiving information from the MCU. The 33982 latches in data from the input shift registers to the addressed registers on the rising edge of CS. The device transfers status information from the power output to the shift register on the falling edge of CS. The SO output driver is enabled when CS is logic [0]. CS should transition from a logic [1] to a logic [0] state only when SCLK is a logic [0]. CS has an internal pull-up, IUP.
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CSB CS SCLK
SI
D7
D6
D5
D4
D3
D2
D1
D0
SO SO
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
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Notes 1. RSTB is in a logic state during the above operation. RST NOTES: 1. RST is a logic [1] 1 stateduring the above operation. 2. D7-D0 relate to the most recentmost recent ordered data of data into the SPSS 2. D0, D1, D2, ..., and D7 relate to the ordered entry of entry into the device. 3. OD7-OD0 OD2, ..., and OD7 relate to of ordered fault and status data out data outdevice. 3. OD0, OD1, relate to the first 8 bits the first 8 bits of ordered fault and status of the of the device.
Figure 7. Single 8-Bit Word SPI Communication
CSB CS
SCLK SCLK
S SI I
D7
D6
D5
D2
D1
D0
D 7*
D 6*
D 5*
D 2*
D1*
D0*
SO SO
OD7
OD6
OD5
OD2
OD1
OD0
D7
D6
D5
D2
D1
D0
R a B is n a lo g ic 1 s t a t e d u in g t h e a b o v e o p e 1. R NOTE : Notes S 1. RST isSSTTlogic i[1] state during ther above operation. r a t i o n . 2. D 0 , D 1 , D 2 , . .. , a n d D 7 r e la t e t o t h e m o s t r e c e n t o r d e r e d e n t r y o f d a t a in t o t h e S P S S 3. O D 0 , O D to the , . . . , n d O D 7 r e la t e o t h e fir t 8 b ts o o r e r e d f a 2. D7-D0 relate 1 , O D 2mostarecent ordered tentry ofsdata iinto f thed device.u l t a n d s t a t u s d a t a o u t o f t h e d e v i c e . 4. O D 0 , O D 1 , O D 2 , .. ., a n d O D 7 r e p r e s e n t t h e f ir s t 8 b its o f o r d e r e d f a u lt a n d s t a t u s d a t a o u t o f t h e S P S S 3. D7*-D0* relate to the previous 8 bits (last command word) of data that was previously shifted into the device. 4. OD7-OD0 relate to the first 8 bits of ordered fault and status data out of the device.
F IG U R E
4b.
M U L T IP L E
8 b it W O R D
S P I C O M M U N IC A T IO N
Figure 8. Multiple 8-Bit Word SPI Communication
Serial Input Communication
SPI communication is accomplished using 8-bit messages. A message is transmitted by the MCU starting with the MSB, D7, and ending with the LSB, D0 (Table 1). Each incoming command message on the SI terminal can be interpreted using the following bit assignments: the MSB (D7) is the watchdog bit and in some cases a register address bit; the next three bits, D6-D4, are used to select the command register; and the remaining four bits, D3-D0, are used to configure and control the output and its protection features. Multiple messages can be transmitted in succession to accommodate those applications where daisy chaining is desirable or to confirm transmitted data as long as the messages are all multiples of eight bits. Any attempt made to latch in a message that is not eight bits will be ignored. The 33982 has defined registers, which are used to configure the device and to control the state of the output. Table 2, page 17, summarizes the SI registers. The registers are addressed via D6-D4 of the incoming SPI word (Table 1).
Bit Sig
Table 1. SI Message Bit Assignment
SI Msg Bit Message Bit Description
MSB
D7
Watchdog in: toggled to satisfy watchdog requirements; also used as a register address bit. Register address bits. Used to configure the inputs, outputs, and the device protection features and SO status content. Used to configure the inputs, outputs, and the device protection features and SO status content.
D6-D4 D3-D1
LSB
D0
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Table 2. Serial Input Address and Configuration Bit Map
SI Register D7 D6 D5 D4 Serial Input Data D3 D2 D1 D0
Table 3. Overcurrent Low Detection Levels
SOCL2 (D2) SOCL1 (D1) SOCL0 (D0) Overcurrent Low Detection (Amperes)
STATR OCR SOCHLR CDTOLR DICR OSDR WDR
x x x x x 0 1 0 1 x
0 0 0 0 1 1 1 1 1 1
0 0 1 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0 0 1
0 0 SOCH OL dis FAST SR 0 0 0 0
SOA2 0 SOCL2 CD dis CSNS high OSD2 0 0 0
SOA1
SOA0
0 0 0 0 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
50 45 40 35 30 25 20 15
CSNS EN IN_SPI SOCL1 OCLT1 IN dis OSD1 WD1 0 UV_dis SOCL0 OCLT0 A/O OSD0 WD0 0 OV_dis
1 1
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NAR UOVR TEST
Table 4. Overcurrent High Detection Levels
SOCH (D3) Overcurrent High Detection (Amperes)
Motorola Internal Use (Test)
x = Don't care.
0 1
150 100
Device Register Addressing
The following section describes the possible register addresses and their impact on device operation. Address x000--Status Register (STATR) The STATR register is used to read the device status and the various configuration register contents without disrupting the device operation or the register contents. The register bits D2, D1, and D0 determine the content of the first eight bits of SO data. In addition to the device status, this feature provides the ability to read the content of the OCR, SOCHLR, CDTOLR, DICR, OSDR, WDR, NAR, and UOVR registers. (Refer to the section entitled Serial Output Communication (Device Status Return Data) beginning on page 18.) Address x001--Output Control Register (OCR) The OCR register allows the MCU to control the output through the SPI. Incoming message bit D0 (IN_SPI) reflects the desired states of the high-side output: a logic [1] enables the output switch and a logic [0] turns it OFF. A logic [1] on message bit D1 enables the Current Sense (CSNS) terminal. Bits D2 and D3 must be logic [0]. Bit D7 is used to feed the watchdog if enabled. Address x010--Select Overcurrent High and Low Register (SOCHLR) The SOCHLR register allows the MCU to configure the output overcurrent low and high detection levels, respectively. In addition to protecting the device, this slow blow fuse emulation feature can be used to optimize the load requirements to match system characteristics. Bits D2-D0 are used to set the overcurrent low detection level to one of eight possible levels are shown in Table 3. Bit D3 is used to set the overcurrent high detection level to one of two levels as outlined in Table 4.
Address x011--Current Detection Time and Open Load Register (CDTOLR) The CDTOLR register is used by the MCU to determine the amount of time the device will allow an overcurrent low condition before output latches OFF occurs. Bits D1 and D0 allow the MCU to select one of four fault blanking times defined in Table 5. Note that these timeouts apply only to the overcurrent low detection levels. If the selected overcurrent high level is reached, the device will latch off within 20 s. Table 5. Overcurrent Low Detection Blanking Time
OCLT[1:0] Timing
00 01 10 11
155 ms 10 ms 1.2 ms 150 s
A logic [1] on bit D2 disables the overcurrent low (CD dis) detection timeout feature. A logic [1] on bit D3 disables the open load (OL) detection feature. Address x100--Direct Input Control Register (DICR) The DICR register is used by the MCU to enable, disable, or configure the direct IN terminal control of the output. A logic [0] on bit D1 will enable the output for direct control by the IN terminal. A logic [1] on bit D1 will disable the output from direct control. While addressing this register, if the input was enabled for direct control, a logic [1] for the D0 bit will result in a Boolean AND of the IN terminal with its corresponding D0 message bit when addressing the OCR register. Similarly, a logic [0] on the D0 terminal will result in a Boolean OR of the IN terminal with
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the corresponding message bits when addressing the OCR register. The DICR register is useful if there is a need to independently turn on and off several loads that are PWM'd at the same frequency and duty cycle with only one PWM signal. This type of operation can be accomplished by connecting the pertinent direct IN terminals of several devices to a PWM output port from the MCU and configuring each of the outputs to be controlled via their respective direct IN terminal. The DICR is then used to Boolean AND the direct IN(s) of each of the outputs with the dedicated SPI bit that also controls the output. Each configured SPI bit can now be used to enable and disable the common PWM signal from controlling its assigned output. A logic [1] on bit D2 is used to select the high ratio (CSR1, 1/40000) on the CSNS terminal. The default value [0] is used to select the low ratio (CSR0, 1/5400). A logic [1] on bit D3 is used to select the high-speed slew rate. The default value [0] corresponds to the low speed slew rate. Address 0101--Output Switching Delay Register (OSDR) The OSDR register is used to configure the device with a programmable time delay that is active during Output On transitions that are initiated via SPI (not via direct input). Whenever the input is commanded to transition from [0] to [1], the output will be held OFF for the time delay configured in the OSDR register. The programming of the contents of this register has no effect on device Fail-Safe mode operation. The default value of the OSDR register is 000, equating to no delay, since the switching delay time is 0 ms. This feature allows the user a way to minimize inrush currents, or surges, thereby allowing loads to be synchronously switched ON with a single command. Table 6 shows the eight selectable output switching delay times, which range from 0 ms to 525 ms. Table 6. Switching Delay
OSD[2:0] (D2, D1, D0) Timing (ms)
toggled as well to ensure that the new timeout period is programmed at the beginning of a new count sequence. Table 7. Watchdog Timeout
WD[1:0] (D1, D0) Timing (ms)
00 01 10 11
620 310 2500 1250
Address 0110--No Action Register (NAR) The NAR register can be used to no-operation fill SPI data packets in a daisy chain SPI configuration. This allows devices to not be affected by commands being clocked over a daisychained SPI configuration, and by toggling the WD bit (D7) the watchdog circuitry will continue to be reset while no programming or data readback functions are being requested from the device. Address 1110--Undervoltage/Overvoltage Register (UOVR) The UOVR register can be used to disable or enable the overvoltage and/or undervoltage protection. By default ([0]), both protections are active. When disabled, an undervoltage or overvoltage condition fault will not be reported in bits D1 and D0 of the output fault register. Address x111--TEST The TEST register is reserved for test and is not accessible with SPI during normal operation.
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Serial Output Communication (Device Status Return Data)
When the CS terminal is pulled low, the output status register is loaded. Meanwhile, the data is clocked out MSB- (OD7-) first as the new message data is clocked into the SI terminal. The first eight bits of data clocking out of the SO, and following a CS transition, are dependant upon the previously written SPI word. Any bits clocked out of the SO terminal after the first eight will be representative of the initial message bits clocked into the SI terminal since the CS terminal first transitioned to a logic [0]. This feature is useful for daisy chaining devices as well as message verification. A valid message length is determined following a CS transition of [0] to [1]. If there is a valid message length, the data is latched into the appropriate registers. A valid message length is a multiple of eight bits. At this time, the SO terminal is tristated and the fault status register is now able to accept new fault status information. The output status register correctly reflects the status of the STATR-selected register data at the time the CS is pulled to a
000 001 010 011 100 101 110 111
0 75 150 225 300 375 450 525
Address 1101--Watchdog Register (WDR) The WDR register is used by the MCU to configure the watchdog timeout. Watchdog timeout is configured using bits D1 and D0 (Table 7). When bits D1and D0 are programmed for the desired watchdog timeout period, the WD bit (D7) should be
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logic [0] during SPI communication and/or for the period of time since the last valid SPI communication, with the following exceptions: * The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid SPI communication never occurred. * Battery transients below 6.0 V resulting in an undervoltage shutdown of the outputs may result in incorrect data loaded into the status register. The SO data transmitted to the MCU during the first SPI communication following an undervoltage VPWR condition should be ignored.
* The RST terminal transition from a logic [0] to [1] while the WAKE terminal is at logic [0] may result in incorrect data loaded into the status register. The SO data transmitted to the MCU during the first SPI communication following this condition should be ignored.
Serial Output Bit Assignment
The eight bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 8 summarizes the SO register content.
Table 8. Serial Output Bit Map Description
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Previous STATR D7, D2, D1, D0 SOA3 SOA2 SOA1 SOA0 OD7 OD6 OD5
Serial Output Returned Data OD4 OD3 OD2 OD1 OD0
x x x x x 0 1 0 1 x
0 0 0 0 1 1 1 1 1 1
0 0 1 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0 0 1
WDin WDin WDin WDin WDin 0 1 0 1 WDin
OTF 0 0 0 1 1 1 1 1 -
OCHF 0 1 1 0 0 0 1 1 -
OCLF 1 0 1 0 1 1 0 0 -
OLF 0 SOCH OL dis Fast SR FSM_HS 0 0 0 -
UVF 0 SOCL2 CD dis CSNS high OSD2 WDTO IN Terminal 0 -
OVF CSNS EN SOCL1 OCLT1 IN dis OSD1 WD1 FSI Terminal UV_dis -
FAULT IN_SPI SOCL0 OCLT0 A/O OSD0 WD0 WAKE Terminal OV_dis -
x = Don't care.
Bit OD7 reflects the state of the watchdog bit (D7) addressed during the prior communication. The contents of bits OD[6:0] depend upon the bits D[2:0] from the most recent STATR command SOA[2:0]. Previous Address SOA[2:0]=000 If the previous three MSBs are 000, bits OD6-OD0 reflect the current state of the fault register (FLTR) (Table 9). Previous Address SOA[2:0]=001 The data in bits OD1 and OD0 contain CSNS EN and IN_SPI programmed bits, respectively. Previous Address SOA[2:0]=010 The data in bit OD3 contain the programmed overcurrent high detection level (refer to Table 4, page 17), and the data in bits OD2, OD1, and OD0 contain the programmed overcurrent low detection levels (refer to Table 3, page 17).
Table 9. Fault Register
OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
x
OTF
OCHF
OCLF
OLF
UVF
OVF
FAULT
OD7 (x) = Don't care. OD6 (OTF) = Overtemperature Flag. OD5 (OCHF) = Overcurrent High Flag. (This fault is latched.) OD4 (OCLF) = Overcurrent Low Flag. (This fault is latched.) OD3 (OLF) = Open Load Flag. OD2 (UVF) = Undervoltage Flag. (This fault is latched or not latched.) OD1 (OVF) = Overvoltage Flag. OD0 (FAULT) = This flag reports a fault and is reset by a read operation.
Note The FS terminal reports a fault and is reset by a new Switch-ON command (via SPI or direct input IN).
Previous Address SOA[2:0]=011 The data returned in bits OD1 and OD0 are current values for the overcurrent fault blanking time, illustrated in Table 5, page 17. Bit OD2 reports when the overcurrent detection timeout feature is active. OD3 reports whether the open load circuitry is active.
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Previous Address SOA[2:0]=100 The returned data contain the programmed values in the DICR. Previous Address SOA[2:0]=101 * SOA3 = 0. The returned data contain the programmed values in the OSDR. Bit OD3 (FSM_HS) reflects the state of the output in the Fail-Safe mode after a watchdog timeout occurs. * SOA3 = 1. The returned data contain the programmed values in the WDR. Bit OD2 (WDTO) reflects the status of the watchdog circuitry. If WDTO bit is [1], the watchdog has timed out and the device is in Fail-Safe mode. If WDTO is [0], the device is in Normal mode (assuming device is powered and not in the Sleep mode), with the watchdog either enabled or disabled.
Previous Address SOA[2:0]=110 * SOA3 = 0. OD2 to OD0 return the state of the IN, FSI, and WAKE terminals, respectively (Table 10). Table 10. Terminal Register
OD2 OD1 OD0
IN Terminal
FSI Terminal
WAKE Terminal
* SOA3 = 1. The returned data contains the programmed values in the UOVR register. Bit OD1 reflects the state of the undervoltage protection, while bit OD0 reflects the state of the overvoltage protection (refer to Table 8, page 19). Previous Address SOA[2:0]=111 Null Data. No previous register Read Back command received, so bits OD2, OD1, and OD0 are null, or 000.
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MODES OF OPERATION
The 33982 has four operating modes. They are Sleep, Normal, Fault, and Fail-Safe. Table 11 summarizes details contained in succeeding paragraphs. Table 11. Fail-Safe Operation and Transitions to Other 33982 Modes
Mode
FS
Sleep Mode
The default mode of the 33982 is the Sleep mode. This is the state of the device after first applying battery voltage (VPWR), prior to any I/O transitions. This is also the state of the device when the WAKE and RST are both logic [0]. In the Sleep mode, the output and all unused internal circuitry, such as the internal 5.0 V regulator, are off to minimize current draw. In addition, all SPI-configurable features of the device are as if set to logic [0]. The device will transition to the Normal or Fail-Safe operating modes based on the WAKE and RST inputs as defined in Table 11.
WAKE
RST
WDTO
Comments
Sleep Normal
x 1 0
0 x 1 x 0 1 0 1
0 1 x 1 1 1 1 0
x No
Device is in Sleep mode. All outputs are OFF. Normal mode. Watchdog is active if enabled. The device is currently in fault mode. The faulted output is OFF. Watchdog has timed out and the device is in FailSafe mode. The output is as configured with the RFS resistor connected to FSI. RST and WAKE must be transitioned to logic [0] simultaneously to bring the device out of the FailSafe mode or momentarily tied the FSI terminal to ground.
Fault
0 1 1 1 1
No
Normal Mode
The 33982 is in Normal mode when: * VPWR is within the normal voltage range. * RST terminal is logic [1]. * No fault has occurred.
FailSafe
Yes
Fail-Safe Mode
Fail-Safe Mode and Watchdog If the FSI input is not grounded, the watchdog timeout detection is active when either the WAKE or RST input terminal transitions from logic [0] to [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting resistance that limits the internal clamp current. The watchdog timeout is a multiple of an internal oscillator and is specified in Table 7, page 18. As long as the WD bit (D7) of an incoming SPI message is toggled within the minimum watchdog timeout period (WDTO), based on the programmed value of the WDR the device will operate normally. If an internal watchdog timeout occurs before the WD bit, the device will revert to a Fail-Safe mode until the device is reinitialized.
x = Don't care.
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During the Fail-Safe mode, the output will be ON or OFF depending upon the resistor RFS connected to the FSI terminal, regardless of the state of the various direct inputs and modes (Table 12). In this mode, the SPI register content is retained except for overcurrent high and low detection levels and timing, which are reset to their default value (SOCL, SOCH, OCLT). The watchdog, overvoltage, overtemperature, and overcurrent circuitry (with default value for this one) are fully operational. Table 12. Output State During Fail-Safe Mode
RFS (k) High-Side State
Overtemperature Fault (Non-Latching) The 33982 incorporates overtemperature detection and shutdown circuitry in the output structure. Overtemperature detection is enabled when the output is in the ON state. For the output, an overtemperature fault (OTF) condition results in the faulted output turning OFF until the temperature falls below the TSD(HYS). This cycle will continue indefinitely until action is taken by the MCU to shut OFF the output, or until the offending load is removed. When experiencing this fault, the OTF fault bit will be set in the status register and cleared after either a valid SPI read or a power reset of the device. Overvoltage Fault (Non-Latching) The 33982 shuts down the output during an overvoltage fault (OVF) condition on the VPWR terminal. The output remains in the OFF state until the overvoltage condition is removed. When experiencing this fault, the OVF fault bit is set in bit OD1 and cleared after either a valid SPI read or a power reset of the device. The overvoltage protection and diagnostic can be disabled through SPI (bit OV_dis). Undervoltage Shutdown (Latching or Non-Latching) The output latches OFF at some battery voltage between 5.0 V and 6.0 V. As long as the VDD level stays within the normal specified range, the internal logic states within the device will be sustained. This ensures that when the battery level then returns above 6.0 V, the device can be returned to the state that it was in prior to the low VPWR excursion. Once the output latches OFF, the outputs must be turned OFF and ON again to re-enable them. In the case IN=0, this fault is nonlatched. The undervoltage protection and diagnostic can be disabled through SPI (bit UV_dis). Open Load Fault (Non-Latching) The 33982 incorporates open load detection circuitry on the output. Output open load fault (OLF) is detected and reported as a fault condition when the output is disabled (OFF). The open load fault is detected and latched into the status register after the internal gate voltage is pulled low enough to turn OFF the output. The OLF fault bit is set in the status register. If the open load fault is removed, the status register will be cleared after reading the register. The open load protection can be disabled through SPI (bit OL_dis).
0 10
Fail-Safe Mode Disabled HS OFF HS ON
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30
The Fail-Safe mode can be detected by monitoring the WDTO bit D2 of the WDR register. This bit is logic [1] when the device is in Fail-Safe mode. The device can be brought out of the Fail-Safe mode by transitioning the WAKE and RST terminals from logic [1] to logic [0] or forcing the FSI terminal to logic [0]. Table 11, page 20, summarizes the various methods for resetting the device from the latched Fail-Safe mode. If the FSI terminal is tied to GND, the Watchdog fail-safe operation is disabled. Loss of VDD If the external 5.0 V supply is not within specification, or even disconnected, all register content is reset. The output can still be driven by the direct input IN. The 33982 uses the battery input to power the output MOSFET-related current sense circuitry and any other internal logic, providing fail-safe device operation with no VDD supplied. In this state, the watchdog, overvoltage, overtemperature, and overcurrent circuitry are fully operational with default values.
Fault Mode
The 33982 indicates the following faults as they occur by driving the FS terminal to [0]: * * * * Overtemperature fault Overvoltage and undervoltage fault Open load fault Overcurrent fault (high and low)
The FS terminal will automatically return to [1] when the fault condition is removed, except for overcurrent and in some cases undervoltage. Fault information is retained in the fault register and is available (and reset) via the SO terminal during the first valid SPI communication (refer to Table 9, page 19).
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Overcurrent Fault (Latching) The 33982 has eight programmable overcurrent low detection levels (IOCL) and two programmable overcurrent high detection levels (IOCH) for maximum device protection. The two selectable, simultaneously active overcurrent detection levels, defined by IOCH and IOCL, are illustrated in Figure 4, page 13. The eight different overcurrent low detection levels (IOCL0, IOCL1, IOCL2, IOCL3, IOCL4, IOCL5, IOCL6, and IOCL7) are likewise illustrated in Figure 4. If the load current level ever reaches the selected overcurrent low detection level and the overcurrent condition exceeds the programmed overcurrent time period (tOCx), the device will latch the output OFF.
For both cases, the device output will stay off indefinitely until the device is commanded OFF and then ON again.
Reverse Battery
The output survives the application of reverse voltage as low as -16 V. Under these conditions, the output's gate is enhanced to keep the junction temperature less than 150C. The ON resistance of the output is fairly similar to that in the Normal mode. No additional passive components are required.
Ground Disconnect Protection
In the event the 33982 ground is disconnected from load ground, the device protects itself and safely turns OFF the output regardless the state of the output at the time of disconnection.
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If at any time the current reaches the selected IOCH level, then the device will immediately latch the fault and turn OFF the output, regardless of the selected tOCL driver.
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PACKAGE DIMENSIONS
PNA SUFFIX 16-TERMINAL PQFN NON-LEADED PACKAGE CASE 1402-02 ISSUE B
12
12 1 2X
A M 0.1 C
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PIN 1 INDEX AREA
12
15
16
M PIN NUMBER REF. ONLY 0.1 C 2.2 2.20 2.0 1.95 0.05 C 4
B
2X
0.1 C
10X
0.6 0.2 0.1 0.05
DETAIL G
M M
0.05 0.00 DETAIL G
VIEW ROTATED 90 CLOCKWISE
C
SEATING PLANE
CAB C
9X
2X
0.95 0.55 0.1 0.05 1.1 0.6
M M
CAB C
1
0.9
2X 1.075
0.1 C A B 5.0 4.6
12
6X
6X
2.05 1.55
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. THE COMPLETE JEDEC DESIGNATOR FOR THIS PACKAGE IS: HF-PQFP-N. 4. COPLANARITY APPLIES TO LEADS AND CORNER LEADS. 5. MINIMUM METAL GAP SHOULD BE 0.25MM.
2.5 2.1 1.45 4X 1.05
13
3.55 5.5 5.1 0.1 C A B 1.85
14
(2)
6X
0.8 0.4 1.28 0.88
(10X 0.25) 2.25 1.75 (2X 0.75)
16
15 2X
(10X 0.4) 0.1 C A B
(0.5) (10X 0.5) 10.7 10.3 0.1 C A B 11.2 10.8 0.1 C A B VIEW M-M
0.15 0.05
6 PLACES
CASE 1402-02
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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33982 23
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appl ication in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective owners. (c) Motorola, Inc. 2004
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